K4S510432B-TCL75 Datasheet PDF (512Mb B-die SDRAM Specification) | Download Samsung semiconductor K4S510432B-TCL75

K4S510432B-TCL75 - 512Mb B-die SDRAM Specification

Description

The K4S510432B / K4S510832B / K4S511632B is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 33,554,432 words by 4 bits / 4 x 16,777,216 words by 8 bits / 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology.

Features

JEDEC standard 3.3V power supply.
LVTTL compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8) -. Burst type (Sequential & Interleave).
All inputs are sampled at the positive going edge of the system clock.
Burst read single-bit write operation.
DQM (x4,x8) & L(U)DQM (x16) for masking.
Auto & self refresh.
64ms refresh peri.

Datasheet Details

Part number	K4S510432B-TCL75
Manufacturer	Samsung semiconductor
File Size	149.53 KB
Description	512Mb B-die SDRAM Specification
Datasheet	K4S510432B-TCL75 Datasheet
Additional preview pages of the K4S510432B-TCL75 datasheet.

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Full PDF Text Transcription

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SDRAM 512Mb B-die (x4, x8, x16) CMOS SDRAM 512Mb B-die SDRAM Specification Revision 1.1 February 2004 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.1 February 2004 SDRAM 512Mb B-die (x4, x8, x16) Revision History Revision 1.0 (January, 2004) - First release. Revision 1.1 (February, 2004) - Corrected typo. CMOS SDRAM Rev. 1.1 February 2004 SDRAM 512Mb B-die (x4, x8, x16) CMOS SDRAM 32M x 4Bit x 4 Banks / 16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks SDRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8) -.

Published: Apr 7, 2005 |